High Bandwidth Memory (HBM)

History

HBM began from the memory bandwidth bottleneck, the "memory wall." William Wulf and Sally McKee coined the concept in 1994, and efforts to solve the problem of processor speed outrunning memory bandwidth gains led to AMD's memory work in the mid-2000s.

Die-stacked memory was first commercialized in flash: Toshiba's 8-die NAND flash chip in April 2007 and Hynix Semiconductor's 24-die NAND chip on 24 September 2007. TSV-based 3D stacked RAM was first commercialized by Elpida Memory, which developed the first 8GB DRAM chip stacking four DDR3 dies in September 2009 and released it in June 2011. In 2011, SK Hynix introduced TSV 16GB DDR3 (40nm-class) and Samsung introduced TSV 32GB DDR3 (30nm-class) in September; in October Samsung and Micron announced the TSV-based Hybrid Memory Cube (HMC).

HBM's own development began at AMD in 2008 with the aim of solving computer memory's power consumption and form factor problems, and a team led by Senior AMD Fellow Bryan Black solved the die-stacking problem. Memory partner SK Hynix took part along with interposer (UMC) and packaging (Amkor, ASE) partners. JEDEC released the Wide IO memory standard JESD229, a predecessor of HBM, in December 2011, and following a 2010 proposal by AMD and SK Hynix the first HBM standard JESD235 was adopted in October 2013. Development was completed that year when SK Hynix built the first HBM memory chip, and high-volume manufacturing began in 2015 at Hynix's Icheon facility in South Korea.

Relations

The JEDEC standardization timeline continued by generation: HBM1 (JESD235) in October 2013, HBM2 (JESD235a) in January 2016, the HBM2E update in late 2018, HBM3 on 27 January 2022, and HBM4 in April 2025. After HBM4, HBM4E, SPHBM4 and zHBM are under development.

Manufacturing and design are highly concentrated. In 2025 the largest HBM manufacturers were SK Hynix, Samsung Electronics and Micron Technology, and the three firms controlled 97% of global HBM wafer production, the outcome of decades of global competition in which Korean and American firms won the lead. TSMC produces the base die for HBM and is planned to be the foundry for several HBM companies in 2026. As of the mid-2020s every major AI chip maker, including Huawei, uses HBM, which is effectively mandatory for high-performance AI accelerators.

South Korea's supply chain is closely tied to the United States. SK Hynix and Samsung supply HBM to U.S. AI hardware leaders such as Nvidia, Microsoft and Broadcom, and most recently Tesla. At the same time, advanced memory semiconductors such as HBM and DDR5 are the central pillar of South Korea's export economy: 2024 semiconductor exports reached $141.9 billion, up 43.9 percent year on year, with China the largest market at $46.6 billion (32.8 percent) and the United States at $10.7 billion (7.5 percent). Interdependence with China is also a risk: as of 2024, 47.5 percent of South Korea's rare earth inputs came from China, which licenses rare-earth and other critical material exports and can trace downstream use.

Examples

The first HBM memory chip was produced by SK Hynix in 2013, and the first GPU using HBM was AMD's Fiji, released in June 2015 and used in the Radeon R9 Fury X. HBM thus spread from consumer gaming to data-center and AI applications: the first data-center GPU adoption was Nvidia's Tesla P100, announced in April 2016, and in 2024 Nvidia announced the Blackwell architecture, which couples each data-center GPU with multiple HBM stacks.

A table of representative generation specifications: HBM1 (2013) 4GB, 128GB/s; HBM2 (2016) 2.4Gb/s, 8GB, 307GB/s; HBM2E (2019) 3.6Gb/s, 24GB, 461GB/s; HBM3 (2022) 6.4Gb/s, 819GB/s; HBM3E (2023) 9.8Gb/s, 48GB, 1229GB/s; HBM4 (2025) 8Gb/s, 32x64-bit, 64GB, 2048GB/s.

Nvidia's H100 GPU used HBM3, and in August 2022 Nvidia said the "Hopper" H100 would provide 80GB RAM and 3TB/s memory bandwidth with five active HBM3 sites. In August 2023 it announced the GH200 Grace Hopper superchip using HBM3e over a 6144-bit bus, with 141GB, 50 percent higher bandwidth and 75 percent higher capacity than the HBM3 version. In 2026 AMD's MI400 series is among the first products to use HBM4.

An HBM1 4-Hi stack has two 128-bit channels per die, 8 channels and 1024 bits in total, and a GPU using four such stacks has a 4096-bit memory bus. Such wide buses drive AI chip performance: as of 2024 HBM accounts for about half the production cost of an AI chip, and a manufacturer stuck with an older HBM generation produces an inferior product no matter how fast the processor is.

Distinctions

HBM achieves higher bandwidth than DDR4 or GDDR5 with less power and a substantially smaller form factor. Its bus is 1024 bits wide against GDDR's 32 bits, but it adds silicon interposer cost and, with so many connections, requires new interconnect methods. Traditional DRAM sits on separate chips linked to the processor through narrow motherboard channels, whereas HBM stacks DRAM dies directly beside the processor on the same interposer and communicates over many more parallel channels.

HBM is incompatible with a similar-in-principle alternative: it resembles the Hybrid Memory Cube (HMC) in principle but does not work with the HMC interface developed by Micron Technology. HBM is also a separately manufactured and separately packaged component from the processor in an AI accelerator, and memory bandwidth constrains overall AI chip performance.

In its market relation to commodity DRAM, HBM crowds out capacity and compresses general-purpose DRAM supply: the conversion ratio between HBM and DDR5 wafer capacity is 3-to-1, so each HBM ramp immediately cuts general-purpose memory supply. China is a latecomer to HBM manufacturing: CXMT, its largest DRAM maker, currently manufactures second-generation HBM chips, the level Korean firms first produced in 2016, and aims to develop HBM roughly three to four years behind SK Hynix, Samsung and Micron by skipping a generation.

The Korean Wikipedia edition names "MI430X" as a first HBM4 product, while the English edition names AMD's 2026 MI400 series. Because the two editions differ on the product name, this entry does not settle it.